Design Verification Lead Job at AMD

AMD Markham, ON

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

THE ROLE:
We are currently looking for Senior ASIC Design Verification Engineers who will be involved in all aspects of AMD's next generation Heterogeneous APU. This includes verifying PCI Express design using latest UVM standard and develop comprehensive testplan to ensure coverage closure. He/She will also apply low power verification methodology and measure overall system performance of our IP. The position allows exposure to all aspect of ASIC design stages. A strong C++/System Verilog language and problem solving skill is required. Good understanding of PCI Express and Computer Architecture is preferred. Other technical knowledge such as Verilog, Perl, and OVL would be beneficial for testbench/simulation debug.

THE PERSON:
Creative and innovator and thinker who loves technical problems and detail-oriented tasks
Exhibits relentless commitment to help the team meet quality and development goals on schedule
Drives to learn and perform at his or her highest potential in a technical capacity
Thrives in both a team environment and in individual contribution
Communicates openly and clearly in meetings, presentations, emails, and reports
Able to learn independently and acquire new skills required for the job
Flexible in working hours to accommodate working with co-workers in different time-zones

KEY RESPONSIBLITIES:
Writing/Implementing/Reviewing Test Plans
Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments
Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM
Analyzing Functional, Code, and Test Plan Coverage
Implementing Assertions, Checkers, and Monitors
Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification
Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
Triaging and Debugging Regressions
Reproducing Functional Bugs found in Silicon in Simulation and/or Formal Verification tools
Conducting and participating in Code Reviews
Technical leadership is an asset, including driving projects from start to the finish and Design verification sign-off

PREFERRED EXPERIENCE:
Digital Design in RTL, Verilog HDL
Testbench Architecture, SystemVerilog, OVM/UVM/VMM
C/C++, Java or other object-oriented programming language
Perl, Ruby, Shell-scripting, UNIX/LINUX Environment
vcs, ncsim, questa, or other simulator and associated waveform viewers such as verdi
PC System Architecture: PCI Express, HyperTransport, x86, ARM
On-Chip Bus Interfaces and Architectures: AMBA AXI, OCP, PIPE
Experience in the ASIC industry including a design verification lead is an asset
Design verification leadership experience a plus.

ACADEMIC CREDENTIALS:
BSc in Electrical or Computer Engineering with 10+ years experience Or MSc in Electrical or Computer Engineering with 7+ years experience

LOCATION: Vancouver/ Markham/ Ottawa/ Calgary

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.


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